Dudekula Sajid Ali

About Me

I’m a pre-final year Electronics and Communication Engineering student at IIITDM Kurnool, and also pursuing a BS in Data Science from IIT Madras. My focus lies in VLSI Design Verification and RTL Design, and I’m currently building hands-on experience with SystemVerilog, UVM, and FPGA tools.

Skills

• Languages: SystemVerilog, Verilog, Python, C++
• Tools: ModelSim, Vivado, Keil, Raspberry Pi
• Domains: Design Verification, Digital Design, RTL Simulation

Projects

Projects will be added here as they are completed. Stay tuned!

Resume

Contact

Email: sajidali24012006@gmail.com

Phone: +91 8688057662